The overall debug, performed at generated RTL level, has been a little bit more complex than with a hand-written RTL (where of course 100% of resources are easy to identify), but all the methods interfaces are visible, all the registers are also visible and clearly identified, only are missing some internal variables, and this is progressing with the last deliveries of the tool. It's not so simple to explain, but as soon as you can split the design in several independant functions, the global behavior will be optimised, taking into account that some actions are sometimes allowed, sometimes not. In addition, because the tool manages the scheduling of atomics parts, it's easy to build mechanisms which can interact between themselves with the maximum efficiency. I designed the more complex parts in a couple of weeks, with a compact code (compared to RTL), which seems easy to configure and to maintain. When I had to design the complex arbitrations and the data streaming, coupled with some weeks of practice, things became easier. I started with the most simple parts of my DMA design, and after 2 or 3 weeks of practice, I'm sure I was more efficient with standard RTL language.
In addition, the tool provides a lot of embedded features which are helpful when correctly managed, but which make the things even more difficult. The new concepts intoduced by the tool (atomic rules and methods scheduled by the tool) are not so easy to handle for someone which is coding in RTL for years.
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